This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 11-268714, filed Sep. 22, 1999; and No. 2000-278705, filed Sep. 13, 2000, the entire contents of which are incorporated herein by reference.
The present invention relates to protection for ESD (Electro Static Discharge) of a semiconductor device, particularly, to a protection circuit against an ESD surge and an external excess voltage using a stacked MOSFET structure.
In the conventional protection circuit of a semiconductor device, a discharging circuit consisting of combination of a diode and a resistor is formed between the input pad and the ground or between the output pad and the ground so as to discharge the static charge accumulated in the pins of the package in the assembling and mounting procedure so as to prevent the electrostatic breakdown.
On the other hand, the scaling is a very effective means for the high integration degree and the high operating speed of an LSI. In accordance with the scaling of the process, the operation voltage is also subjected to the scaling in view of the voltage tolerance.
However, the I/O interface voltage is slow in the progress of the scaling of the power source voltage, compared with the device, with the result that it is highly required that the low operating voltage and the high I/O interface voltage be satisfied simultaneously. An I/O formation technology tolerant to other power sources is known to the art as a technology that satisfies this requirement without giving rise to a process overhead.
In general, in the case of using an output buffer, the external voltage is higher than the internal operation voltage so as to give rise to a problem in respect of the reliability of the gate insulating film. In other words, a reliability problem represented by TDDB (Time-Dependent Dielectric Breakdown) and HCI (Hot Carrier Injection) tends to be generated.
In order to overcome the problem noted above, it was customary in the past to use a protection technology utilizing a stacked structure of MOSFFT""s, as shown in FIG. 1A. For the sake of simplicity, N-channel MOSFET""s alone are stacked in the circuit shown in FIG. 1A. As shown in the drawing, N-channel MOSFET""s Q1 and Q2 are connected in series between a pad 1 of an external power source Vext and the ground (GND) so as to form a stacked structure of MOSFET""s. An internal power source Vint is applied to an internal voltage terminal 2 connected to the gate of the MOSFET Q1. Incidentally, voltage of 0V to Vint is applied to the terminal 2a connected to the gate of the MOSFET Q2.
In the case of using the stacked structure of MOSFET""s shown in FIG. 1A, the gate-drain voltage VGD of the MOSFET and the gate-source voltage VGS of the MOSFET is lower than Vint, i.e., VGD, VGS less than Vint, so as to assure the TDDB reliability. Further, since the drain-source voltage VDS divides Vext, the HCI reliability is also ensured.
Concerning the MOSFET Q2, the drain voltage is held at Vintxe2x88x92Vth, where Vth represents the threshold voltage, so as to avoid the problem in terms of the reliability.
In recent years, in a semiconductor device using a different power source technology provided with the external power source Vext and the internal power source Vint, a protection circuit of I/O""s tolerant to other power sources having a stacked structure of MOSFET""s in which the MOSFET""s Q1 and Q2 are connected in series between the pad 1 and GND is used as a protection circuit exhibiting a high surge tolerance against the surge entering through, for example, the pad 1, as shown in FIGS. 1A and 1B.
FIG. 1B shows the equivalent circuit of FIG. 1A and the problem in the case where a surge voltage V is applied to the pad 1 for a short time. The external surge voltage V enters the pad 1 for various reasons. For example, the external surge voltage is generated in the case of ESD in which the charge added to the surrounding portions in the assembling, testing and mounting steps to a system is discharged through the pins of the package.
In the structure shown in FIGS. 1A and 1B, it is possible for the breakdown of the protection circuit to take place in the case where the surge voltage V is applied for a short time to the pad 1. To be more specific, under the state that, although the gate of the MOSFET Q1 is connected to Vint, the power source is not turned on as shown in FIG. 1A, the gate of the MOSFET Q1 bears the ground potential. In addition, since a very large equivalent capacitance is connected to Vint, the gate-drain voltage VGD of the MOSFET Q1 exceeds the withstand voltage of the gate insulating film during application of the surge voltage V. As a result, the MOSFET Q1 is broken down before the snap-back characteristics of the MOSFET effective for the surge absorption perform their functions.
The breakdown process of the MOSFET Q1 during application of the surge voltage V to the pad 1 will now be described with reference to the equivalent circuit shown in FIG. 1B. If the surge voltage V is applied to the equivalent circuit shown in FIG. 1B, the electron-hole avalanche takes place on the channel surface on the drain side of the MOSFET Q1. As a result, a large current flows between the source and drain of the MOSFET Q1, and the surge voltage applied to the external power source pad 1 is rapidly lowered by the discharge current. It follows that the stacked MOSFET protection circuit exhibits excellent snap-back characteristics.
However, since a high surge voltage V is applied to the stacked MOSFET protection circuit consisting of the MOSFET""s Q1 and Q2, the greatest gate-drain voltage VGD is applied to the drain edge portion of the gate insulating film of the MOSFET Q1 as denoted by a circle 10 of a broken line in FIG. 1B, giving rise to the problem that the gate insulating film is broken down at the portion denoted by the broken circle 10.
On the other hand, it was attempted to use a protection circuit of one stage MOSFET in which the drain of the MOSFET Q2 is connected directly to the pad 1. In the protection circuit of one stage MOSFET, the drain voltage of the MOSFET Q2 is lowered by an amount equal to the source-drain voltage of the MOSFET Q1 so as to lower the maximum gate-drain voltage VGD applied to the drain edge of the gate insulating film of the MOSFET Q2 so as to suppress the breakdown of the gate insulating film.
FIG. 2 compares the snap-back characteristics of the stacked MOSFET protection circuit consisting of the MOSFET""s Q1 and Q2 with those of protection circuit of the one stage MOSFET consisting of the MOSFET Q2 alone.
In FIG. 2, the snap-back voltage of the stacked structure is denoted by VSB, which is denoted by a thick broken line, the drain voltage in the xe2x80x9cONxe2x80x9d state is denoted by VDB. The phenomenon called in general a second breakdown causes the snap-back curves in the transition region in which VSB is switched to VDB to show two steps.
On the other hand, the snap-back voltage VSB, and the drain voltage VDB, under the xe2x80x9cONxe2x80x9d state for the one stage MOSFET, which are denoted by a thin solid curve, are lower than the snap-back voltage VSD and the drain voltage VDB under the xe2x80x9cONxe2x80x9d state, respectively, for the stacked MOSFET structure, which are denoted by a thick broken curve.
If the surge voltage V caused by, for example, ESD is applied to the pad 1, the protection circuit is repeatedly switched along the curves of the snap-back characteristics shown in FIG. 2, with the result that the protection circuit is capable of performing the surge protection of the semiconductor integrated circuit until the breakdown 10 of the gate insulating film shown in FIG. 1B is made unrecoverable.
As described previously, the snap-back voltage VSB, of the conventional one stage MOSFET protection circuit is lower than the snap-back voltage VSB of the protection circuit of the stacked structure so as to produce a merit that the occurrence of the breakdown 10 of the gate insulating film can be suppressed. On the other hand, the conventional one stage MOSFET protection circuit is defective in that it is impossible to set the snap-back voltage VSB, at a sufficiently large value relative to the maximum rating of the external power source voltage required for the reliability assurance of the semiconductor device.
As described above, where a stacked structure of MOSFET""s is used as a protection circuit against ESD, serious problems are left unsolved. In general, similar problems are generated in the case of using a stacked MOSFET protection circuit against the external surge voltage.
As described above, the conventional stacked MOSFET protection circuit is defective in that the gate insulating film of the first MOSFET tends to be broken down at the edge of the drain. Also, the conventional one stage MOSFET protection circuit is defective in that it is incapable of sufficiently assuring the TDDB and HCI reliability of the semiconductor device.
An object of the present invention, which has been achieved in an attempt to overcome the above-noted problems inherent in the prior art, is to provide a stacked MOSFET protection circuit capable of sufficiently assuring the TDDB and HCI reliability of the semiconductor device and capable of avoiding the breakdown of the gate insulating film.
In the protection circuit of the present invention, a clamping circuit consisting of, for example, a clamp diode is connected between the gate and the source of a MOSFET constituting the stacked MOSFET circuit so as to release an excess voltage and, thus, to avoid the breakdown of the gate insulating film caused by application of the excess voltage between the gate and the drain of the MOSFET. The stacked MOSFET protection circuit provided with such a clamping circuit is adapted for a protection circuit against an external surge entering from, particularly, the external power source pad.
The protection circuit of the present invention is also featured in that, in order to avoid the breakdown, caused by the excess voltage, of the gate insulating film of the MOSFET constituting the stacked protection circuit, the circuit is provided with a switching circuit consisting of a diode that is turned on when the excess voltage is applied between the gate and the drain of the MOSFET and a resistor or consisting of a MOSFET and a resistor. The stacked protection circuit of the MOSFET provided with the particular switching circuit is adapted for use as, particularly, a protection circuit of an input/output buffer consisting of MOSFET""s connected to an I/O pad.
According to a first aspect of the present invention, there is provided a protection circuit, comprising first and second MOS transistors having the source of the first MOS transistor connected to the drain of the second MOS transistor; a clamping circuit having first and second terminals, the first terminal being connected to the gate of the first MOS transistor and the second terminal being connected to the drain of the first MOS transistor; and a pad connected to the drain of the first MOS transistor.
It is desirable for the clamping circuit to serve to maintain constant the potential difference between the first and second terminals when the surge voltage enters the pad.
It is desirable for the source and gate of the second MOS transistor to be connected to the ground.
It is desirable for the clamping circuit to consist of a diode. In this case, the cathode of the diode forms the first terminal of the clamping circuit with the anode of the diode forming the second terminal of the clamping circuit.
It is also desirable for the clamping circuit to consist of a plurality of diodes having the cathode of each diode connected to the anode of the adjacent diode, wherein the cathode forming end portion on one side of the plural diodes constitute the first terminal of the clamping circuit, and the anode forming end portion on the other side of the plural diodes constitute the second terminal of the clamping circuit.
According to a second aspect of the present invention, there is provided a protection circuit, comprising first and second MOS transistors having the source of the first MOS transistor connected to the drain of the second MOS transistor; a switching circuit having first, second and third terminals, the first terminal being connected to the gate of the first MOS transistor, the second terminal being connected to the drain of the first MOS transistor, and the third terminal being connected to the internal power source of the semiconductor device, and a pad connected to the drain of the first MOS transistor.
It is desirable for the switching circuit to serve to electrically cut-off the second terminal during the normal operation of the semiconductor device and to maintain constant the potential difference between the first and second terminals when the surge voltage enters the pad.
It is desirable for the switching circuit to consist of a diode. In this case, the cathode of the diode is connected to the gate of the first MOS transistor so as to form the first terminal of the switching circuit, and the anode of the diode forms the second terminal of the switching circuit. Further, the cathode of the diode is connected to the internal power source of the semiconductor device so as to form the third terminal of the switching circuit. More preferably, the cathode of the diode is connected via a resistor circuit to the internal power source of the semiconductor device so as to form the third terminal of the switching circuit.
It is desirable for the switching circuit to consist of a plurality of diodes having the cathode of each diode connected to the anode of the adjacent diode. In this case, the cathode forming end portion on one side of the diodes are connected to the gate of the first MOS transistor so as to form the first terminal of the switching circuit, and the anode forming end portion on the other side of the diodes form the second terminal of the switching circuit. Further, the cathode forming end portion on one side of the diodes are connected to the internal power source of the semiconductor device so as to form the third terminal of the switching circuit. More preferably, the cathode forming end portion on one side of the diodes are connected via a resistor circuit to the internal power source of the semiconductor device so as to form the third terminal of the switching circuit.
More preferably, the number n (n being a natural number) of the plural diodes is selected to meet the relationship n greater than (Vextxe2x88x92Vint)/VF, where Vext denotes the voltage of the external power source of the semiconductor device, Vint denotes the voltage of the internal power source, VF denotes the forward voltage of the diode.
More preferably, the switching circuit consists of a third MOS transistor with an inverse conductivity type of the first and second MOS transistors, wherein the source of the third MOS transistor is connected to the gate of the first MOS transistor so as to form the first terminal of the switching circuit, the drain of the third MOS transistor forms the second terminal of the switching circuit, the source of the third MOS transistor is connected to the gate of the third MOS transistor, and the gate of the third MOS transistor is connected via a resistor to the internal power source of the semiconductor device so as to form the third terminal.
More preferably, the threshold voltage Vth of the third MOS transistor is selected to meet the relationship Vth greater than Vextxe2x88x92Vint, where Vext denotes the voltage of the external power source of the semiconductor device, and Vint denotes the voltage of the internal power source.
Further, according to a third aspect of the present invention, there is provided a protection circuit, comprising first and second MOS transistors of a first conductivity type, third and fourth MOS transistors of a second conductivity type, first and second diodes, first and second resistors, an input/output pad, and first, second and third power sources, wherein:
the source of the first MOS transistor is connected to the drain of the second MOS transistor, the source of the third MOS transistor is connected to the drain of the fourth MOS transistor, and each of the drain of the first MOS transistor and the drain of the third MOS transistor is connected to the input/output pad;
the cathode of the first diode is connected to the gate of the first MOS transistor and to the first power source via the first resistor, the anode of the first diode is connected to the input/output pad, the anode of the second diode is connected to the gate of the third MOS transistor and to the second power source via the second resistor, and the cathode of the second diode is connected to the input/output pad; and
the source of the fourth MOS transistor is connected to the third power source, and the source of the second MOS transistor is connected to the ground.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.